Vaidikalaya

MCQ On Machine Instruction

Q1. Operation code field is present in.
  1. programming language instruction
  2. assembly language instruction
  3. machine language instruction
  4. none of the mentioned

Answer: c, machine language instruction

Solution: Machine language instruction format has one or more fields. The first one is the operation code field.

Q2. A machine language instruction format consists of.
  1. Operand field
  2. Operation code field
  3. Operation code field & operand field
  4. none of the mentioned

Answer: c, Operation code field & operand field

Solution: Machine language instruction format has both the fields.

Q3. The length of the one-byte instruction is.
  1. 2 bytes
  2. 1 byte
  3. 3 bytes
  4. 4 bytes

Answer: b, 1 byte

Solution: This format is only one byte long.

Q4. The instruction format ‘register to register’ has a length of.
  1. 2 bytes
  2. 1 byte
  3. 3 bytes
  4. 4 bytes

Answer: a, 2 bytes

Solution: This format is 2 bytes long.

Q5. The R/M field in a machine instruction format specifies.
  1. another register
  2. another memory location
  3. other operands
  4. all of the mentioned

Answer: d, all of the mentioned

Solution: The LSBs (least significant bits) from 0 to 3 represent R/M field that specifies another register or memory location i.e. the other operand.

Q6. In a machine instruction format, S-bit is the.
  1. status bit
  2. sign bit
  3. sign extension bit
  4. none of the mentioned

Answer: c, sign extension bit

Solution: The S-bit known as sign extension bit is used along with W-bit to show the type of operation.

Q7. The bit which is used by the ‘REP’ instruction is.
  1. W-bit
  2. S-bit
  3. V-bit
  4. Z-bit

Answer: d, Z-bit

Solution: The Z-bit is used by the REP instruction to control the loop.

Q8. If a W-bit value is ‘1’ then the operand is of.
  1. 8 bits
  2. 4 bits
  3. 16 bits
  4. 2 bits

Answer: c, 16 bits

Solution: If W-bit is ‘1’ then the operand is of 16-bits, and if it is ‘0’ then the operand is of 8-bits.

Q9. The instructions which after execution transfer control to the next instruction in the sequence are called.
  1. Sequential control flow instructions
  2. control transfer instructions
  3. Sequential control flow & control transfer instructions
  4. none of the mentioned

Answer: a, Sequential control flow instructions

Solution: The sequential control flow instructions follow sequence order in their execution.

Q10. The instructions that transfer the control to some predefined address or the address specified in the instruction are called as.
  1. sequential control flow instructions
  2. control transfer instructions
  3. sequential control flow & control transfer instructions
  4. none of the mentioned

Answer: b, control transfer instructions

Solution: The control transfer instructions transfer control to the specified address.

Q11. The instruction “JUMP” belongs to.
  1. sequential control flow instructions
  2. control transfer instructions
  3. branch instructions
  4. control transfer & branch instructions

Answer: d, control transfer & branch instructions

Solution: The JUMP instruction transfers the control to the address located in the instruction.

Q12. An n-bit opcode field can represent up to how many distinct operations?.
  1. n
  2. 2n
  3. 2^n
  4. n^2

Answer: c, 2^n

Solution: n bits encode 2^n distinct patterns.

Q13. On a zero-address (stack) machine, arithmetic instructions:.
  1. Require two explicit operands
  2. Use no explicit operands (use top of stack)
  3. Use exactly one explicit operand
  4. Cannot perform arithmetic

Answer: b, Use no explicit operands (use top of stack)

Solution: Stack machines pop operands implicitly from the stack top.

Q14. In a load/store (RISC) architecture, arithmetic instructions typically:.
  1. Access memory directly
  2. Operate only on registers
  3. Use an implicit accumulator
  4. Require microcode

Answer: b, Operate only on registers

Solution: RISC ALU ops read/write only registers; loads/stores move data to/from memory.

Q15. A benefit of fixed-length instructions is:.
  1. Simpler, faster decode and pipelining
  2. Higher code density than variable length
  3. More complex hardware
  4. No alignment requirements

Answer: a, Simpler, faster decode and pipelining

Solution: Uniform length simplifies fetch/align/decode stages.

Q16. A 16-bit instruction with a 6-bit opcode and a 3-bit register field leaves how many bits for an immediate?.
  1. 5
  2. 7
  3. 8
  4. 9

Answer: b, 7

Solution: 16 ? 6 ? 3 = 7 bits remain for the immediate.

Q17. Which of the following is typically a privileged instruction?.
  1. ADD
  2. XOR
  3. Disable interrupts (CLI)
  4. INC

Answer: c, Disable interrupts (CLI)

Solution: Changing interrupt state or MMU requires privileged mode.

Q18. A three-address instruction can specify:.
  1. Up to three explicit operands (e.g., dest, src1, src2)
  2. At most two operands
  3. Only one operand
  4. No operands

Answer: a, Up to three explicit operands (e.g., dest, src1, src2)

Solution: Three-address format encodes destination and two sources.

Q19. A typical compare instruction (CMP R1,R2) does what?.
  1. Stores R1?R2 back into R1
  2. Computes R1?R2, sets flags, stores no result
  3. Adds R1 and R2 and sets flags
  4. Compares memory only, not registers

Answer: b, Computes R1?R2, sets flags, stores no result

Solution: CMP affects condition codes without writing a GPR.

Q20. How many bits are required to address 32 general-purpose registers?.
  1. 4
  2. 5
  3. 6
  4. 32

Answer: b, 5

Solution: 2^5 = 32, so 5 bits select one register.

Q21. Which instruction style tends to offer the highest code density in classic CISC designs?.
  1. Register-register only
  2. Register-memory
  3. Memory-memory
  4. Zero-address (stack)

Answer: c, Memory-memory

Solution: CISC memory-to-memory operations can reduce the number of separate load/store ops.

Q22. On a stack machine, to compute (A?B)×(C+D) you need how many arithmetic instructions?.
  1. 2
  2. 3
  3. 4
  4. 5

Answer: b, 3

Solution: SUB for (A?B), ADD for (C+D), MUL for the product ? 3 ops.